The present invention generally relates to digital image processing, and more particularly to resizing and rotation of digital images.
An example programmable logic device (PLD) is the field programmable gate array (FPGA), first introduced by Xilinx, Inc., in 1985. PLDs such as FPGAs are becoming increasingly popular for use in electronics systems. For example, multimedia communications systems employ FPGAs in large measure for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability.
Advances in semiconductor process technology are delivering FPGAs having logic densities in the range of a million system gates and having operating speeds in excess of 200 MHz. These powerful devices are capable of and have been used to implement digital signal processing (DSP) algorithms which are inherently parallel and normally require multiple DSP microprocessors in order to accommodate the high data rates. It is feasible to implement such algorithms on a single FPGA because such devices offer a programmable architecture.
Image resizing typically involves fractional re-sampling, which can lead to prohibitively large implementations and result in compromises in range and resolution. Polyphase decimators and polyphase interpolators are generally employed for fractional re-sampling, depending on whether an image is being reduced (decimator) or enlarged (interpolator).
In many two-dimensional resizing implementations, an intermediate buffer is disposed between horizontal and vertical filter elements. The structure has considerable memory requirements because the size of the intermediate buffer is doubled relative to the image size to support continuous operation.
Image rotation also involves re-sampling, but is performed on non-integer points. For example, with a center point of an image defined, a single parameter xe2x80xa2 specifies the transformation. The equations below provide the coordinate transformation in terms of rotation of the coordinate axis.
Sx=Dx cos (xe2x80xa2)+Dy sin (xe2x80xa2)
Sy=xe2x88x92Dx sin (xe2x80xa2)+D cos (xe2x80xa2)
where S and D represent source and destination coordinates, respectively.
In an implementation having linear addressing through the destination image, the first step in the rotation algorithm is computation of the source values Sx and Sy. From these values, the neighborhood of pixels is known for the filter operation. The location of the destination pixels in the source pixel matrix also gives the weighting factors for bilinear or bicubic interpolation. The pixel value is then calculated with the weighting factors and pixel values in the neighborhood. The process repeats by incrementing the Dx value and continuing in a raster out format. One drawback of this process is the non-uniform addressing of the source pixels. Essentially, the input memory design must have four times the bandwidth (or 16 for bicubic) because there is no sharing of source pixels between destination pixel operations.
Given the speed and flexibility of FPGAs, it would be desirable to implement image resize and rotation circuitry on an FPGA. However, memory bandwidth and frame latency issues must be factored into any solution.
The invention provides circuit arrangements and methods for real-time image resizing and image rotation. In various embodiments, line buffers are used for storage of lines of pixel values for both resizing and rotation. A first one of the line buffers receives input pixel values, and the line buffers are coupled in a chain such that line buffer i receives pixel values from line buffer ixe2x88x921. The lines of pixel values are moved from line buffer i to line buffer i+1 as the pixel values are processed for resizing or rotation.
The line buffers offer improved performance in real-time image resizing by eliminating the need to re-read sample values from a memory. The line buffers further eliminate the need for the added memory of a double buffering approach and introduce no frame latency. For image rotation, the line buffers allows the source pixels to be shared and linearly addressed in generating destination pixels. This greatly reduces the memory requirements for a given bandwidth requirement.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims which follow.